Difference between revisions of "Tutorials"

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(Created page with '= Drexel VLSI & Architecture Lab Tutorials = == IISWC 2015 == === October 4-6, Atlanta, Georgia, USA === '''''Sigil and SynchroTrace: Communication-Aware Workload Profiling an...')
 
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= Drexel VLSI & Architecture Lab Tutorials =
 
 
 
 
== IISWC 2015 ==
 
== IISWC 2015 ==
 
=== October 4-6, Atlanta, Georgia, USA ===
 
=== October 4-6, Atlanta, Georgia, USA ===

Revision as of 15:08, 10 August 2015

IISWC 2015

October 4-6, Atlanta, Georgia, USA

Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory-NoC Simulation



Topic Outline

Trace capture & analysis for multi-threaded programs, large design space exploration, and insights from workload profiling (e.g. accelerator design via hw/sw co-design and related architectural decisions).

Synopsis

The SynchroTrace simulation framework enables exploration of a large design space.

Sigil is our workload profiling toolset that has enabled SynchroTrace. It captures and classifies a workload's computation and communication operations, and intercepts synchronization actions within threads.

Agenda

This talk aims to