Difference between revisions of "Software"

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== SynchroTrace==
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== GitHUB page ==
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Drexel VANDAL GitHub: https://github.com/VANDAL
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 +
 
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== SynchroTrace ==
 +
[https://github.com/VANDAL/SynchroTrace-gem5 git.io/synchrotrace]
  
 
SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).
 
SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).
  
For details see: [[SynchroTrace]]
+
For details and download information see: [[SynchroTrace]]
 +
 
 +
== Prism ==
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[https://github.com/VANDAL/prism git.io/prism]
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Prism is a super-cool™ framework for easy analysis of applications.
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If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al in an executed program, then check out Prism.
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We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators.
  
 
== SLECTS ==
 
== SLECTS ==
  
 
Implementing a slew-driven clock tree synthesis methodology.
 
Implementing a slew-driven clock tree synthesis methodology.
 
For details see: [[SLECTS]]
 
  
  
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A rotary resonant clock synthesizer in Cadence.
 
A rotary resonant clock synthesizer in Cadence.
 
For details see: [[RotarySynthesizer]]
 

Latest revision as of 20:27, 8 February 2019

GitHUB page

Drexel VANDAL GitHub: https://github.com/VANDAL


SynchroTrace

git.io/synchrotrace

SynchroTrace is a two-step trace-driven simulation methodology that enables efficient design space exploration of computing units (CMPs, MPSoCs, HPC, etc.).

For details and download information see: SynchroTrace

Prism

git.io/prism

Prism is a super-cool™ framework for easy analysis of applications. If you want to easily look at memory operations, function traces, IOPs/FLOPs, et al in an executed program, then check out Prism.

We have used it internally for workload-guided EDA tool flows, on-chip routing, thread-mapping, and in the design of architectural simulators.

SLECTS

Implementing a slew-driven clock tree synthesis methodology.


Rotary Resonant Clock Synthesizer

A rotary resonant clock synthesizer in Cadence.