# Publications

From VLSILab

## Books and Book Chapters

- Ivan S. Kourtev, Baris Taskin and Eby G. Friedman,
*Timing Optimization through Clock Skew Scheduling*, Springer, 2009, ISBN-13: 978-0387710556. - Baris Taskin, Ivan S. Kourtev and Eby G. Friedman,
*System Timing*, Handbook of VLSI, 2nd edition, Editor: W. K. Chen, CRC Publishing, December 2006.

## Journals

- Jianchao Lu and Baris Taskin, "Post-CTS Delay Insertion",
*Journal of VLSI Design*, Volume 2010 (2010), Article ID 451809. - Baris Taskin and I. S. Kourtev, "Multi-Phase Synchronization of Non-Zero Clock Skew Level-Sensitive Circuit",
*International Journal on Circuits, Systems and Computers (JCSC)*, Vol. 18, No. 5, pp. 899--908, July 2009. - Baris Taskin, J. DeMaio, O. Farell, M. Hazeltine, R. Ketner, "Custom Topology Rotary Clock Router",
*ACM Transactions on Design Automation of Electronic Systems (TODAES)*, Vol. 14, No. 3, Article 44, May 2009. - Baris Taskin, A. Chiu, J. Salkind, D. Venutolo, "A Shift-Register Based QCA Memory Architecture",
*ACM Journal on Emerging Technologies and Computation (JETC)*, Vol. 5, No. 1, Article 4, January 2009. - Baris Taskin and Bo Hong, "Improving Line-Based QCA Memory Cell Design Through Dual-Phase Clocking",
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, Vol. 16, No. 12, pp. 1648--1656, December 2008. - Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling",
*IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD)*, Vol. 25, No. 4, pp. 651--663, April 2006. - Baris Taskin and Ivan S. Kourtev, "Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits",
*IEEE Transactions on Very Large Scale Integration (VLSI) Systems*, Vol. 12, No. 1, pp. 12--27, January 2004.

## Conferences

- Jianchao Lu and Baris Taskin, "Clock Tree Synthesis with XOR Gates for Polarity Assignment", to appear in the
*Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, July 2010. - Ankit More and Baris Taskin, "Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs", to appear in the
*Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)*, July 2010. - Ankit More and Baris Taskin, "Wireless Interconnects for Inter-tier Communication on 3-D ICs", to appear in the
*Proceedings of the European Microwave Integrated Circuits Conference (EuMIC)*, September 2010. - Ankit More and Baris Taskin, "Simulation Based Study of Wireless RF Interconnects for Practical CMOS Implementation", to appear in the
*Proceedings of the System Level Interconnect Prediction (SLIP)*, June 2010. - Ankit More and Baris Taskin, "Electromagnetic Compatibility of CMOS On-chip Antennas", to appear in the
*Proceedings of the IEEE AP-S International Symposium on Antennas and Propagation*, July 2010. - Ankit More and Baris Taskin, "Electromagnetic Interaction of On-Chip Antennas and CMOS Metal Layers for Wireless IC Interconnects", to appear in the
*Proceedings of the IEEE/ACM Great Lakes Symposium on VLSI Design (GLSVLSI)*, May 2010. - Ankit More and Baris Taskin, "Leakage Current Analysis for Intra-Chip Wireless Interconnects",
*Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)*, March 2010, pp. 49--53. - Jianchao Lu and Baris Taskin, "Clock Buffer Polarity Assignment Considering Capacitive Load",
*Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)*, March 2010. - Vinayak Honkote and Baris Taskin, "Skew Analysis and Bounded Skew Constraint Methodology for Rotary Clocking Technology",
*Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)*, March 2010, pp. 413--417. - Vinayak Honkote and Baris Taskin, "Analysis, Design and Simulation of Capacitive Load Balanced Rotary Oscillatory Array",
*Proceedings of the International Conference on VLSI Design (VLSID)*, January 2010, pp. 218--223. - Jianchao Lu and Baris Taskin, "Incremental Register Placement for Low Power CTS",
*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, November 2009. - Vinayak Honkote and Baris Taskin, "Skew Analysis and Design Methodologies for Improved Performance of Resonant Clocking",
*Proceedings of the IEEE International SoC Design Conference (ISOCC)*, November 2009, pp. 165--168. - Jianchao Lu and Baris Taskin, "Post-CTS Clock Skew Scheduling with Limited Delay Buffering",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2009, pp. 224--227. - Vinayak Honkote and Baris Taskin, "Design Automation Scheme for Wirelength Analysis of Resonant Clocking Technologies",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2009, pp. 1147--1150. - Vinayak Honkote and Baris Taskin, "Capacitive Load Balancing for Mobius Implementation of Standing Wave Oscillator",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2009, pp. 232--235. - Vinayak Honkote and Baris Taskin, "Zero Clock Skew Synchronization with Rotary Clocking Technology",
*Proceedings of the IEEE International Symposium on Quality Electronic Design (ISQED)*, March 2009, pp. 588--593. - Vinayak Honkote and Baris Taskin, "Custom Rotary Clock Router",
*Proceedings of the IEEE International Conference on Computer Design (ICCD)*, October 2008, pp. 114--119. - Baris Taskin and Jianchao Lu, "Post-CTS Delay Insertion to Fix Timing Violations",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2008, pp. 81--84. - Shannon Kurtas and Baris Taskin, "Statistical Timing Analysis of Nonzero Clock Skew Circuits",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2008, pp. 605--608**Best student paper award nominee**. - Vinayak Honkote and Baris Taskin, "Maze Router Based Scheme for Rotary Clock Router",
*Proceedings of the IEEE International Conference on Midwest Circuits and Systems (MWSCAS)*, August 2008, pp. 442--445. - Baris Taskin, Andy Chiu, Jonathan Salkind, Dan Venutolo, "A Shift-Register Based QCA Memory Architecture",
*Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)*, October 2007, pp. 54--61. - Prawat Nagvajara and Baris Taskin, "Design-for-Debug: A Vital Aspect in Education",
*Proceedings of the International Conference on Microelectronic Systems Education (MSE)*, June 2007, pp. 65--66. - Baris Taskin and Ivan S. Kourtev, "A Timing Optimization Method Based on Clock Skew Scheduling and Partitioning in a Parallel Computing Environment",
*Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)*, August 2006, pp. 486--490. - Baris Taskin, John Wood and Ivan S. Kourtev, "Timing-Driven Physical Design for VLSI Circuits Using Resonant Rotary Clocking",
*Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)*, August 2006, pp. 261--265. - Baris Taskin and Bo Hong, "Dual-Phase Line-Based QCA Memory Design",
*Proceedings of the IEEE Conference on Nanotechnology (IEEE NANO)*, July 2006, pp. 302--305. - Baris Taskin and Ivan S. Kourtev, "Delay Insertion Method in Clock Skew Scheduling",
*Proceedings of the ACM International Symposium on Physical Design (ISPD)*, Apr. 2005, pp. 47--54. - Baris Taskin and Ivan S. Kourtev, "Performance Improvement of Edge-Triggered Sequential Circuits",
*Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)*, December 2004, pp. 607--610. - Baris Taskin and Ivan S. Kourtev, "Advanced Timing of Level-Sensitive Sequential Circuits",
*Proceedings of the IEEE International Conference on Electronics, Circuits and Systems (ICECS)*, December 2004, pp. 603--606. - Baris Taskin and Ivan S. Kourtev, "Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits",
*Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)*, May 2004, Vol. 2, pp. II-617--620. - Baris Taskin and Ivan S. Kourtev, "Performance Optimization of Single-Phase Level-Sensitive Circuits Using Time Borrowing and Non-Zero Clock Skew",
*Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU)*, December 2002, pp. 111--117. - Baris Taskin and Ivan S. Kourtev, "Linear Timing Analysis of SOC Synchronous Circuits with Level-Sensitive Latches",
*Proceedings of the IEEE International ASIC/SOC Conference*, September 2002, pp. 358--362.

## Thesis and Dissertations

- Shannon M. Kurtas, M.S. Thesis,
*Statistical Static Timing Analysis of Nonzero Clock Skew Circuits*, 2007