Drexel VLSI and Architecture Laboratory (VANDAL)
Drexel VLSI and Architecture Laboratory consists of a research group of computer engineers, electrical engineers tackling multiple aspects of design, analysis, implementation of integrated circuits and chip architectures. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VLSI and Architecture group can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VLSI and Architecture group explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning, and Cryptocurrencies. Some of the most exciting projects currently ongoing involve:
1) Charge Recovery Logic, which aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
2) The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
3) The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
4) With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
5) Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
6) Design automation of resonant traveling wave oscillators (RTWOs) operating at frequencies ranging from MHz to GHz in nano-scale CMOS technology nodes. Enhance reliability of RTWOs by accounting for PVT and aging at the design stage.
324 Bossone Research Center
Philadelphia, PA 19104