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=== Other researchers ===
=== Other researchers ===
Revision as of 14:55, 10 January 2019
Drexel VLSI and Architecture Laboratory (VANDAL)
Drexel VANDAL group consists of a research group of computer engineers and electrical engineers tackling high impact engineering problems with the objective of building sophisticated systems.
VANDAL has been home to researchers involved closely with the design, analysis, implementation of integrated circuits, chip architectures and software with a focused goal of implementing sophisticated systems. Suited with industrial design tools for integrated circuits, simulation tools and measurement beds, the VANDAL team can design and test digital and mixed-signal circuitry to verify the functionality of the discovered novel circuit and physical design principles. The group also develops new tools and methodologies to improve application performance and efficiency through optimization of both software and hardware architectures. The VANDAL team explores a gamut of workloads including High-Performance Computing, Data Center, GPU, Machine Learning, and Cryptocurrencies. Some of the most exciting projects currently ongoing involve:
- Charge Recovering Systems for IoT, Bio-Implants and Energy Harvesting: Charge recycling logic typically aims at recycling, or recovering, charge that is usually wasted in normal circuits. Since this charge is recycled, Charge Recovery Circuits consume less energy than standard circuits, allowing, for example, a longer battery life.
- Aging-Resilient IoT Hardware: The VLSI group develops automated mitigation techniques that ensure device operation in the toughest environments. Electronics degrade over time and lead to slower operation including failure to operate. By using predictive models with targeted mitigation techniques, electronic devices maintain their operation for longer periods of time.
- Energy-Efficient Clock Synchronization for Computing Systems: The design of clock networks is integral to ensuring fast performance of integrated circuits. The VLSI lab creates automated tools and design methodologies for the synthesis of exa-scale clock networks that require advanced techniques such as Deep Neural Networks. These tools and design methodologies aid in developing novel clocking techniques such as resonant clocking and wireless interconnects.
- Hardware and Software Co-Design for Exascale Computing Systems: With the growth in the number of cores in chip multi-processors (CMP), it is essential to design for scalable communication interconnects. We explore the modeling and design of networks-on-chips (NoCs) as a fabric interconnecting cores in future high-performance chip multi-processors (CMPs).
- Communication Infrastructure for Chip-Multi-Processors and 5G IoT systems within Smart Office Spaces: Wireless communication on-chip are investigated to replace the resource-demanding, conventional, wire-based interconnect networks within integrated circuits. Wireless communication will provide a solution that is highly scalable into the future for the IC communication challenge, as increases in technology scaling and die size dimensions are forecast by the semiconductor industry.
- Cyber Physical Design Automation of Smart Homes/Smart Cities: Through managing energy efficiency and cost-effectiveness. Building an embedded-system based smart CPS platform for power systems. A modern approach in meeting today’s technological need is to use Internet of Things (IoT). Through adaptive exchange of data, hardware equipments are designed to operate autonomously without human supervision. In assistance of our increasing need in electric power, we design this intelligent agent to manage the operation of electric power distribution. In advancement of our understanding in Cyber-Physical System (CPS), we study the physical limit such systems can be designed to delegate.
324 Bossone Research Center
Philadelphia, PA 19104