Ph.D. in Computer Engineering, 2011 - Present
- Drexel University, Philadelphia, Pennsylvania, USA
B.S. in Electrical and Electronics Engineering, 2011
- Middle East Technical University(METU), Ankara, Turkey
- High-Performance/Low-Power Clock Networks
- Low Swing Clock Trees
- Clock Mesh Synthesis, clock mesh benefits
- Electronic Design Automation(EDA) for VLSI, what is EDA?
- Physical Design of System-on-Chips
- Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", to appear in Elsevier Integration, the VLSI Journal, November 2013.
- Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", to appear in the Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013.
- Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
- Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54 Best Paper Nominee.
- Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley, March 2013.
- Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.
- ECE-C302: Digital Systems Projects (Fall, Spring 2013)
- ECE-C304: Design with Microcontrollers (Winter, Summer 2012,13)
- ENGR-231: Linear Engineering Systems (Spring, Fall 2012)
- ECE-E421: Advanced Electronics I (Fall 2011)
- Please refer to my Weekly Schedule to ask for an appointment
3141 Chestnut Street
Department of ECE
Philadelphia, PA 19104
Linkedin: A. Can Sitik