Difference between revisions of "Can Sitik"

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==Research Interests==
 
==Research Interests==
* High-Performance/Low-Power Clock Networks
 
 
* Low Swing Clock Tree Synthesis
 
* Low Swing Clock Tree Synthesis
 
* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
 
* Clock Mesh Synthesis, [http://www.design-reuse.com/articles/21019/clock-mesh-benefits-analysis.html clock mesh benefits]
 
* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
 
* Electronic Design Automation(EDA) for VLSI, [http://en.wikipedia.org/wiki/Electronic_design_automation what is EDA?]
 +
* Clock Network Design for FinFETs
 
* Physical Design of System-on-Chips
 
* Physical Design of System-on-Chips
  

Revision as of 15:02, 19 February 2014

Can Sitik

Education

Ph.D. in Computer Engineering, 2011 - Present

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2013

Drexel University, Philadelphia, Pennsylvania, USA

B.S. in Electrical and Electronics Engineering, 2011

Middle East Technical University(METU), Ankara, Turkey

Research Interests

  • Low Swing Clock Tree Synthesis
  • Clock Mesh Synthesis, clock mesh benefits
  • Electronic Design Automation(EDA) for VLSI, what is EDA?
  • Clock Network Design for FinFETs
  • Physical Design of System-on-Chips

Curriculum Vitae

Can Sitik CV (Dec 2013)

Publications

  1. Can Sitik and Baris Taskin, "Iterative Skew Minimization for Low Swing Clocks", to appear in Elsevier Integration, the VLSI Journal, November 2013.
  2. Can Sitik, Prawat Nagvajara and Baris Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", to appear in the Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013.
  3. Can Sitik and Baris Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
  4. Can Sitik and Baris Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54 Best Paper Nominee.
  5. Can Sitik and Baris Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley, March 2013.
  6. Can Sitik and Baris Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.

Google Scholar Page

Teaching

Please refer to my Weekly Schedule to ask for an appointment

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104

Email: as3577@drexel.edu

Linkedin: A. Can Sitik