Difference between revisions of "Can Sitik"

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(Education)
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====Conferences====
 
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# W. Liu, E. Salman, C. Sitik and B. Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", to appear in ''Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS)'', May 2016.
 
#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
 
#W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", ''Proceedings of Semiconductor Research Corporation (SRC) TECHCON'', September 2015.
 
#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings  of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.
 
#M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", ''Proceedings  of ACM Great Lakes Symposium on VLSI (GLSVLSI)'', May 2015, pp. 301--306.

Revision as of 22:26, 28 February 2016

Can Sitik

Education

Ph.D. in Computer Engineering, 2011 - 2015

Drexel University, Philadelphia, Pennsylvania, USA

M.S. in Computer Engineering, 2013

Drexel University, Philadelphia, Pennsylvania, USA

B.S. in Electrical and Electronics Engineering, 2011

Middle East Technical University(METU), Ankara, Turkey

Research Interests

  • Low Swing Clock Tree Synthesis
  • Pre- and Post-Si Power and Timing Modeling
  • Clock Mesh Synthesis, clock mesh benefits
  • Electronic Design Automation(EDA) for VLSI, what is EDA?
  • Clock Network Design with FinFETs

Curriculum Vitae

Can Sitik CV (Feb 2015)

Publications

Journals

  1. C. Sitik, E. Salman, L. Filippini, S. J. Yoon and B. Taskin, "FinFET-Based Low Swing Clocking", ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 12, No. 2, Article 13, August 2015.
  2. C. Sitik and B. Taskin, "Iterative Skew Minimization for Low Swing Clocks", Elsevier Integration, The VLSI Journal, Vol. 47, No. 3, pp. 356--364, June 2014.

Conferences

  1. W. Liu, E. Salman, C. Sitik and B. Taskin, "Exploiting Useful Skew in Gated Low Voltage Clock Trees for High Performance", to appear in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2016.
  2. W. Liu, E. Salman, C. Sitik, B. Taskin, S. Sundareswaran and B. Huang, "Circuits and Algorithms to Facilitate Low Swing Clocking in Nanoscale Technologies", Proceedings of Semiconductor Research Corporation (SRC) TECHCON, September 2015.
  3. M. Rathore, W. Liu, E. Salman, C. Sitik and B. Taskin, "A Novel Static D Flip-Flop Topology for Low Swing Clocking", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 301--306.
  4. W. Liu, E. Salman, C. Sitik and B. Taskin, "Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks", Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2015, pp. 283--288.
  5. W. Liu, E. Salman, C. Sitik and B. Taskin, "Enhanced Level Shifter for Multi-Voltage Operation", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2015, pp. 1442--1445.
  6. C. Sitik, S. Lerner and B. Taskin, "Timing Characterization of Clock Buffers for Clock Tree Synthesis", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2014, pp. 230--236.
  7. C. Sitik, L. Filippini, E. Salman and B. Taskin, "High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2014, pp. 498--503.
  8. C. Sitik, P. Nagvajara and B. Taskin, "A Microcontroller-Based Embedded System Design Course with PSoC3", Proceedings of the IEEE International Conference on Microelectronic Systems Education (MSE), June 2013, pp. 28--31.
  9. C. Sitik and B. Taskin, "Multi-Corner Multi-Voltage Domain Clock Mesh Design", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 209--214.
  10. C. Sitik and B. Taskin, "Skew-Bounded Low Swing Clock Tree Optimization", Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI), May 2013, pp. 49--54 Best Paper Nominee.
  11. C. Sitik and B. Taskin, "Implementation of Domain-Specific Clock Meshes for Multi-Voltage SoCs with IC Compiler", Proceedings of Synopsys User Groups Conference (SNUG) Silicon Valley, March 2013.
  12. C. Sitik and B. Taskin, "Multi-Voltage Domain Clock Mesh Design", Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2012, pp. 201--206.

Google Scholar Page

Teaching

Please refer to my Weekly Schedule to ask for an appointment

Contact Information

Address:
3141 Chestnut Street
Department of ECE
Drexel University
Bossone 324
Philadelphia, PA 19104

Email: as3577@drexel.edu

Linkedin: A. Can Sitik