Vasil Pano

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Vasil Pano

Education

PhD in Computer Engineering, 2014 - Present
Drexel University, Philadelphia, PA.
B.S. in Computer Engineering, 2014
Drexel University, Philadelphia, PA.

Research Interests

  • Network on Chip
  • Computer Architecture
  • Memory Coherence Protocols
  • Communication Infrastructure

Curriculum Vitae

Vasil Pano CV (October 2017)

Publications

  1. Vasil Pano, Yuqiao Liu, Isikcan Yilmaz, Ankit More, Baris Taskin and Kapil Dandekar, "Wireless NoCs using Directional and Substrate Propagation Antennas," Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2017.
  2. Vasil Pano, Isikcan Yilmaz, Ankit More and Baris Taskin, "Energy Aware Routing of Multi-Level Network-on-Chip Traffic," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016
  3. Vasil Pano, Isikcan Yilmaz, Yuqiao Liu, Baris Taskin and Kapil Dandekar, "Wireless Network-on-Chip Analysis of Propagation Technique for On-chip Communication," Proceedings of the IEEE International Conference on Computer Design (ICCD), October 2016
  4. Yuqiao Liu, Vasil Pano, Damiano Patron, Kapil Dandekar and Baris Taskin, "Innovative Propagation Mechanism for Inter-chip and Intra-chip Communication," Proceedings of the IEEE Wireless and Microwave Technology Conference (WAMICON), April 2015

Tutorial/Poster Presentations

  1. Vasil Pano and Baris Taskin, "SynchroTrace: Synchronization-aware Architecture-agnostic Traces for Light-Weight Multicore Simulation," Poster presented at Design Automation Conference (DAC), 2016
  2. Vasil Pano, Michael Lui, Mark Hempstead and Baris Taskin, "Sigil and SynchroTrace: Communication-Aware Workload Profiling and Memory–NoC Simulation," Tutorial presented at IEEE International Conference on Computer Design (ICCD), 2015.
  3. Vasil Pano, Scott Lerner and Baris Taskin, "Wireless Network-on-Chip", Poster presented at Mid-Atlantic (ASEE), 2014

Teaching Assistant Coursework

Academic Year 2017-2018
Digital Systems Projects (Fall 2017-2018, Junior Level Class)
Academic Year 2016-2017
Parallel Computer Architecture (Winter 2016-2017, Graduate Level Class)
Digital Logic Design (Spring 2016-2017, Sophomore Level Class)
Systems Programming (Summer 2016-2017, Junior Level Class)
Academic Year 2015-2016
Parallel Computer Architecture (Fall 2015-16, Graduate Level Class)
Computation Lab I (Fall 2015-2016, Freshmen Level Class)
Computation Lab II (Winter 2015-2016, Freshmen Level Class)
Systems Programming (Winter 2015-2016, Junior Level Class)
High Performance Computer Architecture (Spring 2015-2016, Graduate Level Class)
Academic Year 2014-2015
Digital Logic Design (Fall 2014-15, Sophomore Level Class)
Internet Architecture and Protocols (Winter 2014-15, Junior Level Class)
Digital Systems Projects (Spring 2014-15, Junior Level Class)
Systems Programming (Summer 2014-15, Junior Level Class)
Academic Year 2013-2014
Network-on-chip I (Fall 2013-14, Graduate Level Class)
ASIC Design II (Spring 2013-14, Graduate Level Class)

Contact Information

Address:
3141 Chestnut Street
ECE Department, Bossone 405
Drexel University
Philadelphia
Pennsylvania 19104

Email: vasilpano@gmail.com

Linkedin: Vasil Pano