Difference between revisions of "Tutorials:SynchroTrace Sigil IISWC 2016"

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===Topic Outline===
 
===Topic Outline===
  
In this tutorial, we discuss Sigil; a workload profiling toolset that allows architects to explore and investigate sources of performance bottlenecks in current and future systems. Sigil captures platform-independent behavior from workloads which can be used to assist HW/SW partitioning problems and to assist trace-based simulation of multi-threaded workloads on CMPs. This tutorial also presents SynchroTrace, a simulation framework built on top of Sigil to perform trace-based simulation.
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In this tutorial, we discuss the SynchroTrace simulation framework -- a fast trace-driven simulation tool for large design space exploration. The tutorial discusses the two major components of the framework: the trace generation tool, Sigil2, and the architectural simulator, SynchroTraceGen.
  
 
===Synopsis===
 
===Synopsis===
  
<!--
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Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be ''critical'' to extracting the most performance and efficiency out of future architectures. The Drexel VLSI & Architecture Lab has developed a set of tools are required to enable this by extracting information on how cores communicate. Our proposed solutions are [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil], a tool to capture platform-independent communication, and [[SynchroTrace]], a framework which extends Sigil and adds mechanisms to enable simulation of future systems.
Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be ''critical'' to extracting the most performance and efficiency out of future architectures. To enable this understanding, a set of tools are required to extract information on how cores communicate. Our proposed solutions are [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil], a tool to capture platform-independent communication, and [[SynchroTrace]], a framework which extends Sigil and adds mechanisms to enable simulation of future systems.
 
  
In this tutorial we discuss the implementation of our tools to promote confidence in the utility of our tools and we also demonstrate the running of the tools to inform the community of their reliability and applicability.
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In this tutorial we discuss the implementation of our tools and also demonstrate the example use-cases.
  
 
The [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil] tool is written to capture and classify computation operations, communication edges between functions/threads, and intercept synchronization operations in threads; Sigil data give insight into the true costs that exist within a workload. This enables data-driven design decisions and analysis in designing future systems. We discuss how a Shadow memory implementation of Sigil can capture platform-independent data and also briefly discuss how the data can be applied to perform HW/SW partitioning.
 
The [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil] tool is written to capture and classify computation operations, communication edges between functions/threads, and intercept synchronization operations in threads; Sigil data give insight into the true costs that exist within a workload. This enables data-driven design decisions and analysis in designing future systems. We discuss how a Shadow memory implementation of Sigil can capture platform-independent data and also briefly discuss how the data can be applied to perform HW/SW partitioning.
  
 
The [[SynchroTrace]] simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures.  With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.
 
The [[SynchroTrace]] simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures.  With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.
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===Agenda===
 
===Agenda===
  
<!--
 
 
# Overview and welcome
 
# Overview and welcome
 
# Sigil; a Communication-aware workload profiling tool (''45 minutes'')
 
# Sigil; a Communication-aware workload profiling tool (''45 minutes'')
## Capture implementation
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## Trace capture
 
## Running Sigil
 
## Running Sigil
## HW/SW partitioning process
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## HW/SW partitioning example
 
## Example on running post-processing
 
## Example on running post-processing
 
# SynchroTrace (''45 minutes'')
 
# SynchroTrace (''45 minutes'')
## Capturing synchronization in multi-threading
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## SynchroTraceGen: a Sigil extension
## Sigil's intercept mechanism
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## SynchroTraceGen trace format
## Sigil's Trace format
 
 
## Generating traces
 
## Generating traces
 
## SynchroTrace Replay
 
## SynchroTrace Replay
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## Running Sigil and interpreting trace generation
 
## Running Sigil and interpreting trace generation
 
## Running Replay and understanding Replay output
 
## Running Replay and understanding Replay output
-->
 
  
 
===Related Media and Links===
 
===Related Media and Links===

Revision as of 15:22, 29 August 2016

IEEE International Symposium on Workload Characterization (IISWC), 2016

September 25-27, Providence, Rhode Island, USA


Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation

Organizers

Dr. Mark Hempstead, Tufts University

Dr. Baris Taskin, Drexel University

Karthik Sangaiah, Drexel University

Michael Lui, Drexel University

Topic Outline

In this tutorial, we discuss the SynchroTrace simulation framework -- a fast trace-driven simulation tool for large design space exploration. The tutorial discusses the two major components of the framework: the trace generation tool, Sigil2, and the architectural simulator, SynchroTraceGen.

Synopsis

Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be critical to extracting the most performance and efficiency out of future architectures. The Drexel VLSI & Architecture Lab has developed a set of tools are required to enable this by extracting information on how cores communicate. Our proposed solutions are Sigil, a tool to capture platform-independent communication, and SynchroTrace, a framework which extends Sigil and adds mechanisms to enable simulation of future systems.

In this tutorial we discuss the implementation of our tools and also demonstrate the example use-cases.

The Sigil tool is written to capture and classify computation operations, communication edges between functions/threads, and intercept synchronization operations in threads; Sigil data give insight into the true costs that exist within a workload. This enables data-driven design decisions and analysis in designing future systems. We discuss how a Shadow memory implementation of Sigil can capture platform-independent data and also briefly discuss how the data can be applied to perform HW/SW partitioning.

The SynchroTrace simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures. With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.

Agenda

  1. Overview and welcome
  2. Sigil; a Communication-aware workload profiling tool (45 minutes)
    1. Trace capture
    2. Running Sigil
    3. HW/SW partitioning example
    4. Example on running post-processing
  3. SynchroTrace (45 minutes)
    1. SynchroTraceGen: a Sigil extension
    2. SynchroTraceGen trace format
    3. Generating traces
    4. SynchroTrace Replay
    5. Replaying traces
    6. Results from paper: Speedy, yet accurate simulation
  4. Guest Speaker (45 minutes)
  5. Hands-on Sigil
    1. Downloading and installing Sigil
    2. Running Sigil and interpreting output
    3. Running post-processing and parsing
  6. Hands-on SynchroTrace
    1. Downloading and installing SynchroTrace
    2. Running Sigil and interpreting trace generation
    3. Running Replay and understanding Replay output

Related Media and Links

SynchroTrace and Sigil Download