Difference between revisions of "Tutorials:SynchroTrace Sigil IISWC 2016"

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[[Baris Taskin| Dr. Baris Taskin]], ''Drexel University''
 
[[Baris Taskin| Dr. Baris Taskin]], ''Drexel University''
  
[[Paco Sangaiah]], ''Drexel University''
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[[Karthik Sangaiah]], ''Drexel University''
  
 
[[Michael Lui]], ''Drexel University''
 
[[Michael Lui]], ''Drexel University''
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===Synopsis===
 
===Synopsis===
  
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Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be ''critical'' to extracting the most performance and efficiency out of future architectures. To enable this understanding, a set of tools are required to extract information on how cores communicate. Our proposed solutions are [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil], a tool to capture platform-independent communication, and [[SynchroTrace]], a framework which extends Sigil and adds mechanisms to enable simulation of future systems.
 
Current architectures trend towards more cores, including ASIC IPs, general purpose CPUs, and GPUs. Understanding how these cores communicate and interact with each other will be ''critical'' to extracting the most performance and efficiency out of future architectures. To enable this understanding, a set of tools are required to extract information on how cores communicate. Our proposed solutions are [http://dpac.ece.drexel.edu/current-research-projects/sigil/ Sigil], a tool to capture platform-independent communication, and [[SynchroTrace]], a framework which extends Sigil and adds mechanisms to enable simulation of future systems.
  
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The [[SynchroTrace]] simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures.  With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.
 
The [[SynchroTrace]] simulation framework utilizes Sigil's platform-independent traces to quickly explore a design space. Synchronization aware traces and replay of those traces, instead of single-threaded deterministic traces, enables accurate simulation of communication bound architectures.  With the addition of fast trace-driven simulation, SynchroTrace quickly iterates over a large design space and assists with design decisions such as NoC design and memory models. We discuss the intercept mechanism by which the Sigil tool is able to capture synchronization constructs. We will also discuss and demonstrate SynchroTrace's trace capture and simulation mechanisms in detail.
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===Agenda===
 
===Agenda===
  
 
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# Overview and welcome
 
# Overview and welcome
 
# Sigil; a Communication-aware workload profiling tool (''45 minutes'')
 
# Sigil; a Communication-aware workload profiling tool (''45 minutes'')
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## Running Sigil and interpreting trace generation
 
## Running Sigil and interpreting trace generation
 
## Running Replay and understanding Replay output
 
## Running Replay and understanding Replay output
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===Related Media and Links===
 
===Related Media and Links===
 
[https://github.com/dpac-vlsi SynchroTrace and Sigil Download]
 
[https://github.com/dpac-vlsi SynchroTrace and Sigil Download]
  
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[[media:Synchrotrace_tutorial.pdf|SynchroTrace Tutorial Presentation]]
 
[[media:Synchrotrace_tutorial.pdf|SynchroTrace Tutorial Presentation]]
  
 
[[media:Sigil_Tutorial_Slides_ICCD2015.pdf‎|Sigil Tutorial Presentation]]
 
[[media:Sigil_Tutorial_Slides_ICCD2015.pdf‎|Sigil Tutorial Presentation]]
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Revision as of 14:38, 28 August 2016

IEEE International Symposium on Workload Characterization (IISWC), 2016

September 25-27, Providence, Rhode Island, USA


Sigil2 and SynchroTrace: Flexible Workload Profiling and Fast Memory-NoC Simulation

Organizers

Dr. Mark Hempstead, Tufts University

Dr. Baris Taskin, Drexel University

Karthik Sangaiah, Drexel University

Michael Lui, Drexel University

Topic Outline

In this tutorial, we discuss Sigil; a workload profiling toolset that allows architects to explore and investigate sources of performance bottlenecks in current and future systems. Sigil captures platform-independent behavior from workloads which can be used to assist HW/SW partitioning problems and to assist trace-based simulation of multi-threaded workloads on CMPs. This tutorial also presents SynchroTrace, a simulation framework built on top of Sigil to perform trace-based simulation.

Synopsis

Agenda

Related Media and Links

SynchroTrace and Sigil Download