- PhD in Electrical Engineering
- Drexel University, Philadelphia, PA.
I am a Ph.D candidate working with Dr. Baris Taskin and Dr. Mark Hempstead in Drexel VLSI and Architecture Laboratory. My research, aimed at cross-component energy management of mobile platforms, is focused on modelling performance and energy of hardware components, designing metrics to measure energy proportionality and developing energy management algorithms for multi-component devices operating under energy constraints.
I am currently working with cores and memory systems. Our models and algorithms are designed to scale frequency of cores and DRAM to deliver best performance under given energy budget. We consider the impact of scaling frequency of one component on performance and energy of the other component; managing components in isolation may have negative impact on performance and energy of the overall system. My research interests, best described by the picture above, include energy efficient computer architecture, exploring hardware and operating system support to improve energy efficiency, and studying thermal management of mobile systems to better manage available energy resources.
I obtained my Bachelors in Electrical and Electronics Engineering from Birla Institute of Technology and Science (BITS-Pilani), India. Before joining Drexel, I spent two years at Qualcomm as Firmware Engineer. During my tenure at Qualcomm I worked on low power architecture design and evaluation of video accelerators. I joined Drexel in September 2010, as a Master’s student in Computer Engineering and continued my research efforts as a Ph.D student starting from April 2012.
Mobile devices such as laptops, tablets and phones operate on battery with limited capacity. It is imperative that these devices operate under energy constraints in order to improve battery lifetime. My research focus is designing a system that is capable of tuning multiple components of a device simultaneously in order to stay under given energy budget.
I developed a holistic approach that uses energy constraints as input, profiles the application at runtime and using the performance and energy models that I developed, selects the best operating frequency and voltage settings for cores and DRAM. As part of the design:
1) I introduced the concept of inefficiency---used to specify energy constraints to our system (IISWC 2015),
2) developed performance and energy models for core and DRAM that consider the cross-component impact of scaling frequency of one component on the other component's performance and energy (ICCD 2016),
3) designed algorithms capable of efficiently searching the 2-dimensional frequency space with minimum overhead (ICCD 2016) and
4) introduced metrics to measure the energy proportionality of the systems (ICCD 2015). I am currently exploring possible extensions to our system i. by adding further components such as GPU, network etc. and ii. by introducing thermal constraints into our system.
3141 Chestnut Street
ECE Department, Bossone 324
Linkedin: Rizwana Begum